1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor integrated circuit device, and more specifically to a method of fabricating a metal-insulator-metal (MIM) capacitor.
2. Description of the Related Art
Capacitors are critical elements in semiconductor integrated circuits, such as mixed signal, high frequency, analog, or digital circuits. Typically, capacitor structures for semiconductor integrated circuits include metal-insulator-semiconductor (MIS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon (PIP) capacitors. Each of these capacitor structures include at least one silicon layer used as a capacitor electrode.
Nevertheless, the use of a silicon layer for the capacitor electrode may result in a higher series resistance and instability in high frequency circuits. Accordingly, metal-insulator-metal (MIM) capacitors have been developed to provide low series resistance. In addition, for improving element performance, the damascene process has been extensively applied in semiconductor back-end processes. Thus, it is necessary to integrate the method of fabricating capacitors with the damascene process.
Currently, capacitor fabrication integrated with a damascene process is only used for planar-type MIM capacitors, as disclosed for example, in U.S. Pat. No. 6,180,976, and illustrated in FIGS. 1a to 1c. First, referring to FIG. 1a, a substrate 100 is provided, such as a semiconductor substrate. An inter-metal dielectric (IMD) layer 102 is deposited on the substrate 100, wherein a copper lower electrode 103 of the planar-type MIM capacitor is formed in the IMD layer 102 by the damascene process. Then, a capacitor dielectric layer 106 and a metal layer 108 are deposited on the IMD layer 102 in order. A photoresist layer 110 is formed on the metal layer 108 to define an upper electrode of the subsequently formed planar-type MIM capacitor.
Subsequently, referring to FIG. 1b, the photoresist layer 110 is patterned by lithography to expose a portion of the metal layer 108. The metal layer 108 uncovered by the photoresist layer 110a and the capacitor dielectric layer 106 are then etched. The remaining metal layer 108a is the upper electrode of the planar-type MIM capacitor.
Finally, referring to FIG. 1c, the planar-type MIM capacitor is formed, after removing the patterned photoresist layer 110a. The above described fabrication process includes more than one instance of lithography, thus, numerous photomasks are required, thereby increasing complexity and process cost.
Planar-type MIM capacitors cannot provide a larger effective electrode area to obtain larger capacitance for high-density future generation integrated circuits due to limited space on a wafer. Further, conductive plugs connecting the upper and lower electrodes of the planar-type MIM capacitor with peripheral devices cross through numerous metal or dielectric layers in the semiconductor structure. Accordingly, it is difficult to achieve process flexibility, such as modifying the layout of a photomask, as it will affect the fabrication of numerous layers simultaneously.
Conventional fabrication of metal interconnects requires a specific distance of at least 1000 Å be maintained between interconnects to avoid shorts. Thus, as shown in FIG. 4, a conventionally fabricated comb-type vertical MIM capacitor occupies the majority of a wafer and substantially reduces the available area thereon. In FIG. 4, 402 represents a capacitor dielectric layer, 404 represents an upper electrode, and 406 represents a lower electrode.